1. Field of the Invention
The invention generally relates to semiconductor memory devices. Specifically, the invention relates to reducing power consumption in semiconductor memory devices.
2. Description of the Related Art
Modern semiconductor memory devices are typically used in a wide variety of electronic devices such as portable data assistants (PDAs), cell phones, and the like. Because the electronic devices are typically powered by batteries, there is a desire to reduce power consumption of the memory devices.
One type of memory device with reduced power consumption is a twin cell dynamic random access memory (twin cell DRAM). FIG. 1 is a circuit diagram depicting an exemplary memory cell 100 of a twin cell DRAM. As depicted, the memory cell 100 may contain two NMOS access transistors 112, 114 which are used to access two capacitors 122, 124 which store data for the memory cell 100. The NMOS transistors 112, 114 may be controlled by a wordline WL 106 connected to the gates of the transistors 112, 114. The memory cell 100 typically stores a binary bit of information and a complement of the bit (e.g., a ‘0 and 1’, respectively, or a ‘1’ and a ‘0’, respectively). The bit and the complement of the bit may be stored as charges in the capacitors 122, 124. When the memory cell 100 is accessed, the stored bit and the complement of the bit may be output on a bitline (bitline true, BLt) 104 and a complementary bitline (BLc) 102, respectively.
FIG. 2 is a timing diagram depicting an exemplary access of the memory cell 100. At some time T0 before the access, the wordline voltage VWL may be a low voltage (e.g., a ground voltage VGND or a wordline off voltage VWLOFF), thereby disconnecting capacitors 122, 124 from the bitlines 102, 104. In some cases, VWLOFF may be a low voltage which is boosted downward by a charge pump. As depicted, a high voltage (VNT=VCC) representing a logic value ‘1’ may be stored in the “true” capacitor 122 of the memory cell 100 and a low voltage (VNC=VGND) representing a logic value ‘0’ may be stored in the complementary capacitor 124.
Before the memory cell 100 is accessed, the bitlines 102, 104 may be precharged (also referred to as equalized) to a precharge voltage (the equalize voltage, VBLEQ). Precharging may be performed to equalize a voltage level remaining on the bitlines 102, 104 from a previous access which used the bitlines 102, 104. Precharging prevents destruction of data stored in the memory cell 100 and allows the small voltage signals used to store information in the memory cell 100 to be properly sensed.
The access of the memory cell 100 may begin at time T1 when VWL is asserted to the wordline on voltage VWLON. VWLON may be sufficient to turn the NMOS transistors 112, 114 on (e.g., to place the transistors 112, 114 in a conducting state). In some cases, VWLON may be a high voltage (VPP) which is boosted upward by a charge pump. When the NMOS transistors 112, 114 are turned on, the voltages VNT, VNC stored in the capacitors 122, 124 may be driven onto the bitlines 102, 104, thereby pulling VNT down and VNC up towards VBLEQ. As the voltages stored in the capacitors 122, 124 are driven onto the bitlines 102, 104, a voltage difference (VBLT−VBLC) between the voltage of the true (VBLT) and complementary (VBLC) bitlines 122, 124 may be created, e.g., by time T2.
At time T3, a sense amplifier connected to the bitlines 102, 104 may be enabled. The sense amplifier may be used to sense and amplify the voltage difference VBLT−VBLC created by the memory cell 100 on the bitlines 102, 104. Thus, at time T3 and continuing to time T4, the voltage difference VBLT−VBLC may be amplified, driving VBLT upwards to the bitline high voltage (VBLH) and driving VBLC downwards to the bitline low voltage (VBLL). Because the transistors 112, 114 may continue to be turned on (e.g., because VWL=VWLON), VNT may also be driven upwards to VBLH while VNC is driven downwards to VBLL. In some cases, the voltages stored in VNT and VNC deteriorate over time, e.g., due to leakage from the memory cell 100. However, when the depicted access is performed and VNT is driven to VBLH and VNC is driven to VBLL (or vice versa), the values stored by the capacitors 122, 124 in the memory cell 100 are refreshed.
At time T5, VWL may be lowered (e.g., to VWLOFF or VGND), thereby disconnecting the capacitors 122, 124 from the bitlines 102, 104 and completing the access. Later, at time T6, the bitlines 102, 104 may be precharged by driving VBLT and VBLC to VBLEQ, thereby preparing the bitlines 102, 104 for a subsequent access.
In some cases, leakage mechanisms in the memory cell 100 may increase the power consumption of the memory device. In low power applications, reducing such leakage mechanisms may become important. One example of a leakage mechanism is a bitline-wordline (BL-WL) short 130, depicted in FIG. 1, formed between a bitline and a wordline. When the bitlines 102, 104 are precharged (e.g., as depicted at time T0) to VBLEQ and the wordline voltage is lowered (deactivating the wordline 106), a voltage difference VWL−VBLC =VBLEQ−VWLOFF (or VWL−VBLC=VBLEQ−VGND) may develop across the short 130, causing current to flow across the short 130 between the wordline 106 and bitline 102, thereby consuming power.
Another example of a leakage mechanism which may occur during precharge is diffusion leakage (also referred to as junction leakage). Diffusion leakage may be cause by a diffusion leakage current (IL) from a junction, for example, a source of a transistor which is turned off, into a well or substrate in which the junction is located. The leakage current is similar to a reverse-biased diode leakage, with the junction and the well forming the reverse-biased diode.
As depicted in FIG. 1, the junction leakage IL may flow from the bitline side of transistors 112, 114 to the bitlines 102, 104. During precharge, the voltage drop from across the junction from the bitlines 102, 104 to the substrate may be VBLEQ−VBB, where VBB is the back bias voltage of the transistor 112, 114. In some cases, VBB may be a low voltage (e.g., VGND) or a downward driven low voltage (e.g., a voltage lower than VGND). Because the junction leakage may be proportional to the junction voltage (VBLEQ−VBB, during precharge), the junction leakage current, and thus the power consumption, during precharge may be substantial.
As described above, the bitlines 102, 104 in the memory device may be precharged between accesses, e.g., during a standby mode. In some cases, the memory device may spend a majority of the time in standby mode (with the bitlines 102, 104 being precharged), e.g., while waiting for user input to the electronic device containing the memory device. Accordingly, the current consumption during precharge and/or a standby mode, typically classified as standby current, is an important parameter in low power memory devices.
Accordingly, what is needed is a method and apparatus for reducing power consumption of a memory device.